Download The Architecture of High Performance Computers by Roland N. Ibbett (auth.) PDF

By Roland N. Ibbett (auth.)

Introduction 1. 1 historic advancements 1 1. 2 innovations for bettering functionality 2 1. three An Architectural layout instance three 2 directions and Addresses 2. 1 Three-address platforms - The CDC 6600 and 7600 7 2. 2 Two-address structures - The IBM System/360 and /370 10 2. three One-address platforms 12 2. four Zero-address platforms 15 2. five The MU5 guide Set 17 2. 6 evaluating guideline codecs 22 three garage Hierarcbies three. 1 shop Interleaving 26 three. 2 The Atlas Paging approach 29 three. three IBM Cache structures 33 three. four The MU5 identify shop 37 three. five info Transfers within the MU5 garage Hierarchy forty four four Pipelines four. 1 The MU5 fundamental Operand Unit Pipeline forty nine four. 2 mathematics Pipelines - The TI ASC sixty two four. three The IBM System/360 version ninety one universal information Bus sixty seven five guide Buffering five. 1 The IBM System/360 version 195 guide Processor seventy two five. 2 guideline Buffering in CDC pcs seventy seven five. three The MU5 guideline Buffer Unit eighty two five. four The CRAY-1 guide Buffers 87 five. five place of the regulate aspect 89 6 Parallel practical devices 6. 1 The CDC 6600 significant Processor ninety five 6. 2 The CDC 7600 vital Processor 104 6. three functionality a hundred and ten 6 • four The CRA Y-1 112 7 Vector Processors 7. 1 Vector amenities in MU5 126 7. 2 String Operations in MU5 136 7. three The CDC Star-100 142 7. four The CDC CYBER 205 146 7.

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Gi yen the same instruction and operand accessing rates, all three systems would have very similar performances, and we would be back where we started, with the intuitive feelings of the designer deciding the ultimate choice. 3 Storage Hierarchies Storage hierarchies have existed for as long as stored program computers themselves. 75K words. Initially users were required to organise their own store transfers between a selected drum track and a selected pair of Williams Tubes, but the Mark 1 Autocode system introduced in 1954 carried out these tasks automatically on behalf of users and so made the two levels of storage appear to them as a one-Ievel store.

3 show the progress of one instruction through the PROP pipeline. It is first copied into DF and DN (function and name respecti vely) and the Decode 0 logic carries out the decoding of the instruction necessary to control the first stage. The decoding logic of figure 4. 1 is spread out in the pipelined version into separate decoders for each stage. dcessary decoding cannot be carried out in sufficient time to control the action of a gi yen stage. In these cases it is carried out in the previous stage, and the various control signals appear as additional function digits, along with the original function, as inputs to the stage requiring them.

24 The Architecture of High Performance Computers The static code space requirements for the CFA programs run on MU5/2 and MU5/3 were not found to be significantly different from those for MU5, whereas the numbers of instructions executed were. The two-address version required roughly three-quarters as many instructions to be obeyed as the one-address version, and the three-address version only half as many. 97 times as many. Clearly, neither of these figures differs significantly from the one-address figures, al though the differences which do exist are in close agreement with the static code requirements.

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